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LTC3834-1 30A IQ Synchronous Step-Down Controller
FEATURES

DESCRIPTIO
Wide Output Voltage Range: 0.8V V OUT 10V Low Operating IQ: 30A OPTI-LOOP(R) Compensation Minimizes COUT 1% Output Voltage Accuracy Wide VIN Range: 4V to 36V Phase-Lockable Fixed Frequency 140kHz to 650kHz Dual N-Channel MOSFET Synchronous Drive Very Low Dropout Operation: 99% Duty Cycle Adjustable Output Voltage Soft-Start or Tracking Output Current Foldback Limiting Output Overvoltage Protection Low Shutdown IQ: 4A Selectable Continuous, Pulse-Skipping or Burst Mode(R) Operation at Light Loads Small 16-Lead Narrow SSOP or 5mm x 3mm DFN Package
The LTC(R)3834-1 is a high performance step-down switching regulator controller that drives an all N-channel synchronous power MOSFET stage. A constant-frequency current mode architecture allows a phase-lockable frequency of up to 650kHz. The 30A no-load quiescent current extends operating life in battery powered systems. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The LTC3834-1 features a precision 0.8V reference . The 4V to 36V input supply range encompasses a wide range of battery chemistries. The TRACK/SS pin ramps the output voltage during startup. Current foldback limits MOSFET heat dissipation during short-circuit conditions. An enhanced feature set part (LTC3834) is available.
Comparison of LTC3834 and LTC3834-1
PART # LTC3834 LTC3834-1 CLKOUT/ PHASMD YES NO EXTVCC YES NO PGOOD YES NO PACKAGES FE20/4 x 5 QFN GN16/3 x 5 DFN
APPLICATIO S

Automotive Systems Telecom Systems Battery-Operated Digital Devices Distributed DC Power Systems
, LT, LTC, LTM, Burst Mode, PolyPhase and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131.
TYPICAL APPLICATIO
PLLLPF 0.01F RUN TRACK/SS BOOST ITH 560pF 54.2k 150pF SGND 68.1k PLLIN/MODE VFB 215k SENSE- SENSE+ PGND BG INTVCC LTC3834-1 SW VIN TG
High Efficiency Step-Down Converter
100
10F 0.22F VIN 4V TO 36V
90 80 70
EFFICIENCY (%)
3.3H
0.012
VOUT 3.3V 5A
60 50 40 30 20 10
150F 4.7F
0 0.000001
38341 TA01
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Efficiency and Power Loss vs Load Current
10000 1000
POWER LOSS (mW)
U
U
100
10
1
0.1 0.0001 0.01 OUTPUT CURRENT (A) 1
38341 TA01b
38341f
1
LTC3834-1
ABSOLUTE
(Note 1)
AXI U
RATI GS
Peak Output Current <10s (TG, BG) ......................... 3A INTVCC Peak Output Current ................................ 50mA Operating Temperature Range (Note 2) .. - 40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (GN Package, Soldering, 10 sec) ...................... 300C
Input Supply Voltage (VIN).........................36V to - 0.3V Top Side Driver Voltage (BOOST) ..............42V to - 0.3V Switch Voltage (SW) ....................................36V to - 5V INTVCC, (BOOST-SW).................................8.5V to - 0.3V RUN, TRACK/SS ......................................... 7V to - 0.3V SENSE+, SENSE- Voltages .........................11V to - 0.3V PLLIN/MODE, PLLLPF ......................... INTVCC to - 0.3V ITH, VFB Voltages .......................................2.7V to - 0.3V
PI CO FIGURATIO
TOP VIEW PLLLPF ITH TRACK/SS VFB SGND PGND BG INTVCC 1 2 3 4 5 6 7 8 17
16 PLLIN/MODE 15 SENSE+ 14 SENSE- 13 RUN 12 BOOST 11 TG 10 SW 9 VIN
DHC PACKAGE 16-Pin (5mm x 3mm) PLASTIC DFN
TJMAX = 125C, JA = 43.5C/W EXPOSED PAD (PIN 17) IS SGND MUST BE SOLDERED TO PCB
ORDER I FOR ATIO
LEAD FREE FINISH LTC3834EDHC-1#PBF LTC3834IDHC-1#PBF LTC3834EGN-1#PBF LTC3834IGN-1#PBF
TAPE AND REEL LTC3834EDHC-1#TRPBF LTC3834IDHC-1#TRPBF LTC3834EGN-1#TRPBF LTC3834IGN-1#TRPBF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VRUN = 5V unless otherwise noted.
SYMBOL VFB IVFB VREFLNREG PARAMETER Regulated Feedback Voltage Feedback Current Reference Voltage Line Regulation CONDITIONS (Note 4); ITH Voltage = 1.2V (Note 4) VIN = 4V to 30V (Note 4)
ELECTRICAL CHARACTERISTICS
Main Control Loop 0.792 0.800 -5 0.002 0.808 - 50 0.02 V nA %/V
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W
W
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TOP VIEW PLLLPF ITH TRACK/SS VFB SGND PGND BG INTVCC 1 2 3 4 5 6 7 8 16 PLLIN/MODE 15 SENSE+ 14 SENSE- 13 RUN 12 BOOST 11 TG 10 SW 9 VIN
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 150C, JA = 90C/W
PART MARKING* 38341 38341 38341 38341
PACKAGE DESCRIPTION 16-Lead (5mm x 3mm) Plastic DFN 16-Lead (5mm x 3mm) Plastic DFN 16-Lead Plastic SSOP 16-Lead Plastic SSOP
TEMPERATURE RANGE -40C to 85C (Note 2) -40C to 85C -40C to 85C (Note 2) -40C to 85C
MIN
TYP
MAX
UNITS
LTC3834-1
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 12V, VRUN = 5V unless otherwise noted.
SYMBOL VLOADREG PARAMETER Output Voltage Load Regulation CONDITIONS (Note 4) Measured in Servo Loop; I TH Voltage = 1.2V to 0.7V Measured in Servo Loop; I TH Voltage = 1.2V to 2V ITH = 1.2V; Sink/Source 5A (Note 4) (Note 5) RUN = 5V, VFB = 0.83V (No Load) VRUN = 0V VIN Ramping Down Measured at VFB Relative to Regulated VFB VSENSE- = VSENSE+ = 0V In Dropout VTRACK = 0V VRUN1, VRUN2 Rising VFB = 0.7V, VSENSE- = 3.3V (Note 6) CLOAD = 3300pF CLOAD = 3300pF (Note 6) CLOAD = 3300pF CLOAD = 3300pF

ELECTRICAL CHARACTERISTICS
MIN
TYP 0.1 - 0.1 0.5 30 4 3.7
MAX 0.5 - 0.5
UNITS % % mmho
gm IQ
Transconductance Amplifier gm Input DC Supply Current Sleep Mode Shutdown Undervoltage Lockout Feedback Overvoltage Lockout Sense Pins Total Source Current Maximum Duty Factor Soft-Start Charge Current RUN Pin ON Threshold Maximum Current Sense Threshold TG Transition Time: Rise Time Fall Time BG Transition Time: Rise Time Fall Time
50 10 4 12
A A V % A %
UVLO VOVL ISENSE DFMAX ITRACK/SS VRUN ON VSENSE(MAX) TG1, 2 tr TG1, 2 tf BG1, 2 tr BG1, 2 tf TG/BG t1D BG/TG t2D tON(MIN) VINTVCCVIN VLDOVIN fNOM fLOW fHIGH fSYNCMIN fSYNCMAX I PLLLPF
8 98 0.85 0.5 85
10 -220 99.4 1.1 0.7 100 50 50 40 40 70 70 200
1.45 0.9 115 90 90 90 80
A V mV ns ns ns ns ns ns ns
Top Gate Off to Bottom Gate On Delay CLOAD = 3300pF Synchronous Switch-On Delay Time Bottom Gate Off to Top Gate On Delay CLOAD = 3300pF Top Switch-On Delay Time Minimum On-Time Internal VCC Voltage INTVCC Load Regulation Nominal Frequency Lowest Frequency Highest Frequency (Note 7) 8.5V < VIN < 30V ICC = 0mA to 20mA VPLLLPF = No Connect VPLLLPF = 0V VPLLLPF = INTVCC 360 220 475 650 5.0
INTVCC Linear Regulator 5.25 0.2 400 250 530 115 800 -5 5 5.5 1.0 440 280 580 140 V % kHz kHz kHz kHz kHz A A
Oscillator and Phase-Locked Loop
Minimum Synchronizable Frequency PLLIN/MODE = External Clock; VPLLLPF = 0V Maximum Synchronizable Frequency PLLIN/MODE = External Clock; VPLLLPF = 2V Phase Detector Output Current Sinking Capability Sourcing Capability fPLLIN/MODE < fOSC fPLLIN/MODE > fOSC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3834E-1 is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3834I-1 is guaranteed to meet performance specifications over the -40C to 85C operating temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC3834GN-1: TJ = TA + (PD * 90C/W) LTC3834DHC-1: TJ = TA + (PD * 43.5C/W)
Note 4: The LTC3834-1 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of IMAX (see Minimum On-Time Considerations in the Applications Information section).
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LTC3834-1 TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency and Power Loss vs Output Current
100 90 80 70
EFFICIENCY (%)
Burst Mode OPERATION FORCED CONTINUOUS MODE PULSE SKIPPING MODE VIN = 12V VOUT = 3.3V
60 50 40 30 20 10 FIGURE 10 CIRCUIT 0.0001 0.01 OUTPUT CURRENT (A) 1
100
EFFICIENCY (%)
EFFICIENCY (%)
0 0.000001
Load Step (Burst Mode Operation)
VOUT 100mV/DIV AC COUPLED
IL 2A/DIV
20s/DIV VOUT = 3.3V FIGURE 10 CIRCUIT
Inductor Current at Light Load
FORCED CONTINUOUS MODE
2A/DIV Burst Mode OPERATION
PULSE SKIPPING MODE 2s/DIV VOUT = 3.3V ILOAD = 100A FIGURE 10 CIRCUIT
38341 G07
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UW
TA = 25C, unless otherwise noted.
Efficiency vs Load Current
10000
100 90 80 70 60 50
82
Efficiency vs Input Voltage
98 96 94 92 90 88 86 84 VOUT = 3.3V FIGURE 10 CIRCUIT 80 0
38341 G02
1000
POWER LOSS (mW)
VIN = 12V VIN = 5V VOUT = 3.3V
10
1
0.1
40 0.000001
FIGURE 10 CIRCUIT 0.0001 0.01 OUTPUT CURRENT (A) 1
5
10
15 20 25 30 INPUT VOLTAGE (V)
35
40
38341 G01
38341 G03
Load Step (Forced Continuous Mode)
VOUT 100mV/DIV AC COUPLED VOUT 100mV/DIV AC COUPLED
Load Step (Pulse Skipping Mode)
IL 2A/DIV
IL 2A/DIV
38341 G04
20s/DIV VOUT = 3.3V FIGURE 10 CIRCUIT
38341 G05
20s/DIV VOUT = 3.3V FIGURE 10 CIRCUIT
38341 G06
Soft Start-Up
Tracking Start-Up
MASTER 2V/DIV
VOUT 1V/DIV
VOUT 2V/DIV
20ms/DIV FIGURE 10 CIRCUIT
38341 G08
20ms/DIV FIGURE 10 CIRCUIT
38341 G09
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LTC3834-1 TYPICAL PERFOR A CE CHARACTERISTICS
Total Input Supply Current vs Input Voltage
350 FIGURE 10 CIRCUIT 300
SUPPLY CURRENT (A)
INTVCC VOLTAGE (V)
5.4 5.2 5.0 4.8 4.6 4.4 4.2
INTVCC
INTVCC VOLTAGE (V)
250 200 150 100 50 0 5 10 20 25 15 INPUT VOLTAGE (V) 30 35
38341 G10
300A LOAD
NO LOAD
Maximum Current Sense Voltage vs ITH Voltage Cycle
100 CURRENT SENSE THRESHOLD (mV) 80 6O 40 20 0 -20 -40 0 0.2 10% DUTY CYCLE 1.0 0.4 0.6 0.8 ITH PIN VOLTAGE (V) 1.2 1.4 FORCED CONTINUOUS Burst Mode OPERATION (RISING) Burst Mode OPERATION (FALLING) PULSE SKIPPING 60 30 0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
INPUT BIAS CURRENT (A)
Foldback Current Limit
MAXIMUM CURRENT SENSE VOLTAGE (mV) 120 100 40 38
QUIESCENT CURRENT (A)
80 60 40 20
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FEEDBACK VOLTAGE (V)
38341 G16
UW
38341 G13
TA = 25C, unless otherwise noted.
INTVCC Voltages vs Temperature
6.0 5.8 5.6
5.4 5.5
INTVCC Line Regulation
5.3
5.2
5.1
4.0 -45
5.0
-25
35 55 -5 15 TEMPERATURE (C)
75
95
0
5
10
15 20 25 30 INPUT VOLTAGE (V)
35
40
38341 G11
38341 G12
SENSE Pins Total Input Bias Current
120 100 80 60 40 20 0
Maximum Current Sense Threshold vs Duty
-30 -60 -90 -120 -150 -180 -210 -240 -270 -300 0 123456789 VSENSE COMMON MODE VOLTAGE (V) 10
0
10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%)
38341 G15
38341 G14
Quiescent Current vs Temperature
36 34 32 30 28 26 24 22 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90
38341zz G17
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LTC3834-1 TYPICAL PERFOR A CE CHARACTERISTICS
SENSE Pins Total Input Bias Current vs ITH
4 1.30 1.25
RUN PIN VOLTAGE (V)
0 15 30 45 60 TEMPERATURE (C) 75 90
INPUT CURRENT (A)
3
TRACK/SS CURRENT (A)
2
1
0 0 0.2
0.4 0.6 0.8 1.0 ITH VOLTAGE (V)
Regulated Feedback Voltage vs Temperature
808 60 30 806 0 804 802 800 798 796 794 792 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90 -30 -60 -90 -120 -150 -180 -210 -240 -270
REGULATED FEEDBACK VOLTAGE (mV)
INPUT CURRENT (A)
INPUT CURRENT (A)
Oscillator Frequency vs Temperature
800 700 VPLLLPF = INTVCC VPLLLPF = FLOAT VPLLLPF = GND 4.2 4.1 4.0
INT VCC VOLTAGE (V)
600
FREQUENCY (kHz)
500 400 300 200 100 0 -45 -25 35 55 -5 15 TEMPERATURE (C) 75 95
6
UW
1.2
TA = 25C, unless otherwise noted. Shutdown (RUN) Threshold vs Temperature
1.00 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60
TRACK/SS Pull-Up Current vs Temperature
1.20 1.15 1.10 1.05 1.00 0.95
0.55 0.50 -45 -30 -15 0 15 30 45 60 TEMPERATURE (C) 75 90
1.4
0.90 -45 -30 -15
38341 G18
38341 G19
38341 G20
SENSE Pins Total Input Bias Current vs Temperature
VOUT = 10V VOUT = 3.3V
Shutdown Current vs Input Voltage
12 10 8 6 4 2 0 5 10 15 20 25 INPUT VOLTAGE (V) 30 35
VOUT = 0V
-300 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
38341 G21
38341 G22
38341 G23
Undervoltage Lockout Threshold vs Temperature
3.9 3.8 3.7 3.6 3.5 3.4 3.3
RISING
FALLING
3.2 -45 -30 -15
0 15 30 45 60 TEMPERATURE (C)
75
90
38341 G24
38341 G25
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LTC3834-1 TYPICAL PERFOR A CE CHARACTERISTICS
INTVCC vs Load Current
5.3 5.2
INTVCC VOLTAGE (V)
SHUTDOWN CURRENT (A)
5.1 5.0 4.9 4.8 4.7 4.6 0 10 40 20 30 LOAD CURRENT (mA) 50 60
PI FU CTIO S (DHC Package/GN Package)
PLLLPF (Pin 1/Pin 1): The phase-locked loop's lowpass filter is tied to this pin when synchronizing to an external clock. Alternatively, tie this pin to GND, INTVCC or leave floating to select 250kHz, 530kHz or 400kHz switching frequency. ITH (Pin 2/Pin 2): Error Amplifier Outputs and Switching Regulator Compensation Points. The current comparator trip point increases with this control voltage. TRACK/SS (Pin 3/Pin 3): External Tracking and SoftStart Input. The LTC3834-1 regulates the VFB voltage to the smaller of 0.8V or the voltage on the TRACK/ SS pin. A internal 1A pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. Alternatively, a resistor divider on another voltage supply connected to this pin allows the LTC3834-1 output to track the other supply during startup. VFB (Pin 4/Pin 4): Receives the remotely sensed feedback voltage from an external resistive divider across the output. SGND (Pin 5/Pin 5): Small Signal Ground. Must be routed separately from high current grounds to the common (-) terminals of the input capacitor. PGND (Pin 6/Pin 6): Driver Power Ground. Connects to the source of bottom (synchronous) N-channel MOSFET, anode of the Schottky rectifier and the (-) terminal of CIN. BG (Pin 7/Pin 7): High Current Gate Drive for Bottom (Synchronous) N-Channel MOSFET. Voltage swing at this pin is from ground to INTVCC. INTVCC (Pin 8/Pin 8): Output of the Internal Linear Low Dropout Regulator. The driver and control circuits are powered from this voltage source. Must be decoupled to power ground with a minimum of 4.7F tantalum or ceramic capacitor. VIN (Pin 9/Pin 9): Main Supply Pin. A bypass capacitor should be tied between this pin and the signal ground pin. SW (Pin 10/Pin 10): Switch Node Connections to Inductor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN. TG (Pin 11/Pin 11): High Current Gate Drive for Top NChannel MOSFET. These are the outputs of floating drivers with a voltage swing equal to INTVCC - 0.5V superimposed on the switch node voltage SW. BOOST (Pin 12/Pin 12): Bootstrapped Supply to the Top Side Floating Driver. A capacitor is connected between the BOOST and SW pins and a Schottky diode is tied between the BOOST and INTVCC pins. Voltage swing at the BOOST pin is from INTVCC to (VIN + INTVCC). RUN (Pin 13/Pin 13): Digital Run Control Input for Controller. Forcing this pin below 0.7V shuts down all control38341f
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TA = 25C, unless otherwise noted. Shutdown Current vs Temperature
7 6 5 4 3 2 1 0 -45 -30 -15
VIN = 12V
0 15 30 45 60 TEMPERATURE (C)
75
90
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LTC3834-1
PI FU CTIO S (DHC Package/GN Package)
ler functions, reducing the quiescent current that the LTC3834-1 draws to approximately 4A. SENSE- (Pin 14/Pin 14): The (-) Input to the Differential Current Comparator. SENSE+ (Pin 15/Pin 15): The (+) Input to the Differential Current Comparator. The ITH pin voltage and controlled offsets between the SENSE- and SENSE+ pins in conjunction with RSENSE set the current trip threshold. PLLIN/MODE (Pin 16/Pin 16): External Synchronization Input to Phase Detector and Forced Continuous Control Input. When an external clock is applied to this pin, the phase-locked loop will force the rising TG signal to be synchronized with the rising edge of the external clock. In this case, an R-C filter must be connected to the PLLLPF pin. When not synchronizing to an external clock, this input determines how the LTC3834-1 operates at light loads. Pulling this pin below 0.7V selects Burst Mode operation. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to a voltage greater than 0.9V and less than INTVCC selects pulseskipping operation. Exposed Pad (Pin 17, DHC Package): SGND. Must be soldered to PCB.
FU CTIO AL DIAGRA
PLLIN/MODE FIN PHASE DET
RLP PLLLPF CLK OSCILLATOR CLP S R INTVCC-0.5V - + PLLIN/MODE 0.8V - + BURSTEN FC BURSTEN 0.4V + - B SLEEP SHDN Q Q DROP OUT DET TOP BOT TOP ON SWITCH LOGIC BOT INTVCC FC
VIN VIN
LDO 5.25V INTVCC
+
SGND INTERNAL SUPPLY RUN
8
W
U
U
U
U
U
INTVCC DB
VIN
BOOST
CB TG D SW CIN
BG PGND
COUT VOUT
L RSENSE
ICMP
+ -
-
++
6mV
-
- +
IR SENSE + SENSE -
0.45V 2(VFB) SLOPE COMP
- EA + OV 0.5A + -
VFB TRACK/SS 0.80V
VFB
RB
RA
0.88V ITH
CC
6V 1A TRACK/SS
CC2
RC
SHDN CSS
3834-1 FD
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LTC3834-1
OPERATIO
Main Control Loop The LTC3834-1 uses a constant-frequency, current mode step-down architecture. During normal operation, each external top MOSFET is turned on when the clock sets the RS latch, and is turned off when the main current comparator, ICMP, resets the RS latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The error amplifier compares the output voltage feedback signal at the VFB pin, (which is generated with an external resistor divider connected across the output voltage, VOUT, to ground) to the internal 0.800V reference voltage. When the load current increases, it causes a slight decrease in VFB relative to the reference, which cause the EA to increase the ITH voltage until the average inductor current matches the new load current. After the top MOSFET is turned off each cycle, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current comparator IR, or the beginning of the next clock cycle. INTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. An internal 5.25V low dropout linear regulator supplies INTVCC power from VIN. The top MOSFET driver is biased from the floating bootstrap capacitor CB, which normally recharges during each off cycle through an external diode when the top MOSFET turns off. If the input voltage VIN decreases to a voltage close to VOUT, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about one twelfth of the clock period every tenth cycle to allow CB to recharge.
U
(Refer to Functional Diagram)
Shutdown and Start-Up (RUN and TRACK/SS Pins) The LTC3834-1 can be shut down using the RUN pin. Pulling this pin below 0.7V shuts down the main control loop for the controller. A low disables the controller and most internal circuits, including the INTVCC regulator, at which time the LTC3834-1 draws only 4A of quiescent current. Releasing the RUN pin allows an internal 0.5A current to pull up the pin and enable that controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the Absolute Maximum rating of 7V on this pin. The start-up of the output voltage VOUT is controlled by the voltage on the TRACK/SS pin. When the voltage on the TRACK/SS pin is less than the 0.8V internal reference, the LTC3834-1 regulates the VFB voltage to the TRACK/SS pin voltage instead of the 0.8V reference. This allows the TRACK/SS pin to be used to program a soft-start by connecting an external capacitor from the TRACK/SS pin to SGND. An internal 1A pull-up current charges this capacitor creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively the TRACK/SS pin can be used to cause the start-up of VOUT to "track" that of another supply. Typically, this requires connecting to the TRACK/SS pin an external resistor divider from the other supply to ground (see Applications Information section). When the RUN pin is pulled low to disable the LTC38341, or when VIN drops below its undervoltage lockout threshold of 3.5V, the TRACK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, the controller is disabled and the external MOSFETs are held off.
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LTC3834-1
OPERATIO
Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction) (PLLIN/MODE Pin) The LTC3834-1 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/MODE pin to a DC voltage below 0.8V (e.g., SGND). To select forced continuous operation, tie the PLLIN/ MODE pin to INTVCC. To select pulse-skipping mode, tie the PLLIN/MODE pin to a DC voltage greater than 0.8V and less than INTVCC - 0.5V. When the LTC3834-1 is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-tenth of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is lower than the load current, the error amplifier EA will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.4V, the internal sleep signal goes high (enabling "sleep" mode) and both external MOSFETs are turned off. The I TH pin is then disconnected from the output of the EA and "parked" at 0.425V. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3834-1 draws to only 30A. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA's output begins to rise. When the output voltage drops enough, the ITH pin is reconnected to the output of the EA, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When the LTC3834-1 is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IR) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative, thus operating in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst
10
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(Refer to Functional Diagram)
Mode operation. However, continuous operation has the advantages of lower output ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current. When the PLLIN/MODE pin is connected for pulse-skipping mode or clocked by an external clock source to use the phase-locked loop (see Frequency Selection and PhaseLocked Loop section), the LTC3834-1 operates in PWM pulse-skipping mode at light loads. In this mode, constant-frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (PLLLPF and PLLIN/MODE Pins) The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the LTC3834-1's controllers can be selected using the PLLLPF pin. If the PLLIN/MODE pin is not being driven by an external clock source, the PLLLPF pin can be floated, tied to INTVCC, or tied to SGND to select 400kHz, 530kHz, or 250kHz, respectively. A phase-locked loop (PLL) is available on the LTC3834-1 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/MODE pin. In this case, a series R-C should be connected between the PLLLPF pin and SGND to serve as the PLL's loop filter. The LTC3834-1 phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of the external top MOSFET to the rising edge of the synchronizing signal.
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OPERATIO
The typical capture range of the LTC3834-1's phaselocked loop is from approximately 115kHz to 800kHz, with a guarantee to be between 140kHz and 650kHz. In other words, the LTC3834-1's PLL is guaranteed to lock to an external clock source whose frequency is between 140kHz and 650kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling).
APPLICATIO S I FOR ATIO
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current. The current comparator has a maximum threshold of 100mV/RSENSE and an input common mode range of SGND to 10V. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, I L. Allowing a margin for variations in the IC and external component values yields:
RSENSE =
80mV IMAX
When using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. A curve is provided to estimate this reduction in peak output current level depending upon the operating duty factor. Operating Frequency and Synchronization The choice of operating frequency, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current.
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(Refer to Functional Diagram)
Output Overvoltage Protection An overvoltage comparator guards against transient overshoots as well as other more serious conditions that may overvoltage the output. When the VFB pin rises to more than 10% higher than its regulation point of 0.800V, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared.
The internal oscillator of the LTC3834-1 runs at a nominal 400kHz frequency when the PLLLPF pin is left floating and the PLLIN/MODE pin is a DC low or high. Pulling the PLLLPF to INTVCC selects 530kHz operation; pulling the PLLLPF to SGND selects 250kHz operation. Alternatively, the LTC3834-1 will phase-lock to a clock signal applied to the PLLIN/MODE pin with a frequency between 140kHz and 650kHz (see Phase-Locked Loop and Frequency Synchronization). Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current I L decreases with higher inductance or frequency and increases with higher VIN:
IL =
V 1 VOUT 1 - OUT ( f)(L) VIN
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Accepting larger values of I L allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is I L=0.3(IMAX). The maximum I L occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 10% of the current limit determined by RSENSE. Lower inductor values (higher I L) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!
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Power MOSFET and Schottky Diode (Optional) Selection Two external power MOSFETs must be selected for each controller in the LTC3834-1: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the INTVCC voltage. This voltage is typically 5V during start-up (see EXTVCC Pin Connection). Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers' data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the Gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by:
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Main Switch Duty Cycle =
VOUT VIN VIN - VOUT VIN
Synchronous Switch Duty Cycle =
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The MOSFET power dissipations at maximum output current are given by:
PMAIN = VOUT (IMAX )2 (1+ T )RDS(ON) + VIN
A ( VIN )2 IM2 X (RDR )(CMILLER ) *
1 1 + ( f) VINTVCC - VTHMIN VTHMIN
PSYNC =
VIN - VOUT (IMAX )2 (1+ T )RDS(ON) VIN
where is the temperature dependency of RDS(ON) and RDR (approximately 2 ) is the effective driver resistance at the MOSFET's Miller threshold voltage. VTHMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1+T) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. The optional Schottky diode D1 shown in Figure 8 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead-time and requiring a reverse recovery period that
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could cost as much as 3% in efficiency at high VIN. A 1A to 3A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS IMAX VOUT VIN - VOUT VIN
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[( )(
)]
1/ 2
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3834-1, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple ( V OUT) is approximated by:
1 VOUT IRIPPLE ESR + 8 fCOUT
where f is the operating frequency, COUT is the output capacitance and IRIPPLE is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage.
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Setting Output Voltage
INPUT BIAS CURRENT (A)
The LTC3834-1 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 1. The regulated output voltage is determined by:
VOUT R = 0.8V * 1+ B RA
To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor and the SW line.
VOUT
LTC3834-1 VFB
RB
CFF
RA
3834-1 F01
Figure 1. Setting Output Voltage
SENSE+ and SENSE- Pins The common mode input range of the current comparator is from 0V to 10V. Continuous linear operation is provided throughout this range allowing output voltages from 0.8V to 10V. The input stage of the current comparator requires that current either be sourced or sunk from the SENSE pins depending on the output voltage, as shown in the curve in Figure 2. If the output voltage is below 1.5V, current will flow out of both SENSE pins to the main output. In these cases, the output can be easily pre-loaded by the VOUT resistor divider to compensate for the current comparator's negative input bias current. Since VFB is servoed to the 0.8V reference voltage, RA in Figure 1 should be chosen to be less than 0.8V/ISENSE, with ISENSE determined from Figure 2 at the specified output voltage.
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60 30 0 -30 -60 -90 -120 -150 -180 -210 -240 -270 -300 0 123456789 VSENSE COMMON MODE VOLTAGE (V) 10
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Figure 2. SENSE Pins Input Bias Current vs Common Mode (Output) Voltage
Tracking and Soft-Start (TRACK/SS Pin) The start-up of VOUT is controlled by the voltage on the TRACK/SS pin. When the voltage on the TRACK/SS pin is less than the internal 0.8V reference, the LTC3834-1 regulates the VFB pin voltage to the voltage on the TRACK/ SS pin instead of 0.8V. The TRACK/SS pin can be used to program an external soft-start function or to allow VOUT to "track" another supply during start-up.
LTC3834-1 TRACK/SS SGND
3834-1 F03
Figure 3. Using the TRACK/SS Pin to Program Soft-Start
Soft-start is enabled by simply connecting a capacitor from the TRACK/SS pin to ground, as shown in Figure 3. An internal 1A current source charges up the capacitor, providing a linear ramping voltage at the TRACK/SS pin. The LTC3834-1 will regulate the VFB pin (and hence VOUT) according to the voltage on the TRACK/SS pin, allowing VOUT to rise smoothly from 0V to its final regulated value. The total soft-start time will be approximately:
t SS = C SS *
0 . 8V 1 A
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Alternatively, the TRACK/SS pin can be used to track two (or more) supplies during start-up, as shown qualitatively in Figures 4a and 4b. To do this, a resistor divider should be connected from the master supply (VX) to the TRACK/ SS pin of the slave supply (VOUT), as shown in Figure 5. During start-up VOUT will track VX according to the ratio set by the resistor divider:
VX RA R + R TRACKB = * TRACKA VOUT R TRACKA R A + RB
For coincident tracking (VOUT = VX during start-up), RA = RTRACKA RB = RTRACKB
VX (MASTER)
OUTPUT VOLTAGE
VOUT (SLAVE)
OUTPUT VOLTAGE
TIME
3834-1 F04A
(4a) Coincident Tracking
Figure 4. Two Different Modes of Output Voltage Tracking
Vx
Figure 5. Using the TRACK/SS Pin for Tracking
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INTVCC Regulator The LTC3834-1 features an internal P-channel low dropout linear regulator (LDO) that supplies power at the INTVCC pin from the VIN supply pin. INTVCC powers the gate drivers and much of the LTC3834-1's internal circuitry. The VIN LDO regulates the voltage at the INTVCC pin to 5.25V. It can supply a peak current of 50mA and must be bypassed to ground with a minimum of 4.7F ceramic capacitor. The ceramic capacitor placed directly adjacent to the INTVCC and PGND IC pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers and to prevent interaction between the channels.
VX (MASTER) VOUT (SLAVE) TIME
3834-1 F04B
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(4b) Ratiometric Tracking
VOUT RB RA RTRACKB TRACK/SS RTRACKA
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High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3834-1 to be exceeded. The INTVCC current, which is dominated by the gate charge current, is supplied by the 5.25V VIN LDO. Power dissipation for the IC in this case is equal to VIN * IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC3834-1 INTVCC current is limited to less than 25mA from a 24V supply when in the GN package: TJ = 70C + (25mA)(24V)(90C/W) = 125C To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (PLLIN/MODE = INTVCC) at maximum VIN. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors CB connected to the BOOST pins supply the gate drive voltages for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. When one of the topside MOSFET is to be turned on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VINTVCC. The value of the boost capacitor CB needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external Schottky diode must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then the efficiency has improved. If there is no change in input current, then there is no change in efficiency.
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Fault Conditions: Current Limit and Current Foldback The LTC3834-1 includes current foldback to help limit load current when the output is shorted to ground. If the output falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100mV to 30mV. Under short-circuit conditions with very low duty cycles, the LTC3834-1 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC3834-1 ( 200ns), the input voltage and induct-or value: I
L(SC) = tON(MIN)
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(VIN/L)
The resulting short-circuit current is:
ISC =
30mV 1 - IL(SC) R SENSE 2
Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator (OV) detects overvoltage faults greater than 10% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage.
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Phase-Locked Loop and Frequency Synchronization The LTC3834-1 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET to be locked to the rising edge of an external clock signal applied to the PLLIN/MODE pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock.
900 800 700 FREQUENCY (kHz) 600 500 400 300 200 100 0 0 0.5 1.0 2.0 1.5 PLLLPF VOLTAGE (V) 2.5
3834 G28
Figure 6. Relationship Between Oscillator Frequency and Voltage at the PLLLPF Pin When Synchronizing to an External Clock
PLLIN/ MODE EXTERNAL OSCILLATOR
DIGITAL PHASE/ FREQUENCY DETECTOR
Figure 7. Phase-Locked Loop Block Diagram
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The output of the phase detector is a pair of complementary current sources that charge or discharge the external filter network connected to the PLLLPF pin. The relationship between the voltage on the PLLLPF pin and operating frequency, when there is a clock signal applied to PLLIN/ MODE, is shown in Figure 6 and specified in the Electrical Characteristics table. Note that the LTC3834-1 can only be synchronized to an external clock whose frequency is within range of the LTC3834-1's internal VCO, which is nominally 115kHz to 800kHz. This is guaranteed to be between 140kHz and 650kHz. A simplified block diagram is shown in Figure 7.
2.4V RLP CLP PLLLPF OSCILLATOR
3834-1 F07
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If the external clock frequency is greater than the internal oscillator's frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the PLLLPF pin is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor CLP holds the voltage. The loop filter components, CLP and RLP, smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP = 10k and CLP is 2200pF to 0.01F. Typically, the external clock (on PLLIN/MODE pin) input high threshold is 1.6V, while the input low threshold is 1.2V. Table 1 summarizes the different states in which the PLLLPF pin can be used.
Table 1
PLLLPF PIN 0V Floating INTVCC RC Loop Filter PLLIN/MODE PIN DC Voltage DC Voltage DC Voltage Clock Signal FREQUENCY 250kHz 400kHz 530kHz Phase-Locked to External Clock
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Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3834-1 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that
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t ON(MIN) <
VOUT VIN( f)
If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3834-1 is approximately 200ns. However, as the peak sense voltage decreases the minimum on-time gradually increases up to about 250ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple.
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Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3834-1 circuits: 1) IC VIN current, 2) INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current has two components: the first is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents; the second is the current drawn from the 3.3V linear regulator output. VIN current typically results in a small (<0.1%) loss. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG =f(QT+QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor, and input and output capacitor ESR. In continuous mode the average output current flows through L and
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RSENSE, but is "chopped" between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 30m , R L = 50m , R SENSE = 10m and R ESR = 40m (sum of both input and output capacitance losses), then the total resistance is 130m . This results in losses ranging from 3% to 13% as the output current increases from 1A to 5A for a 5V output, or a 4% to 20% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the topside MOSFET(s), and become significant only when operating at high input voltages (typically 15V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f Other "hidden" losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these "system" level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20F to 40F of capacitance having a maximum of 20m to 50m of ESR. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss.
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Checking Transient Response
The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to I LOAD (ESR), where ESR is the effective series resistance of COUT. I LOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in Figure 10 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop
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gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 * CLOAD. Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA.
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Design Example As a design example, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A, and f = 250kHz. The inductance value is chosen first based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLLPF pin to GND, generating 250kHz operation. The minimum inductance for 30% ripple current is:
IL = VOUT VOUT 1- V ( f)(L) IN
A 4.7H inductor will produce 23% ripple current and a 3.3H will result in 33%. The peak inductor current will be the maximum DC value plus one half the ripple current, or 5.84A, for the 3.3H value. Increasing the ripple current will also help ensure that the minimum on-time of 180ns is not violated. The minimum on-time occurs at maximum VIN: t ON(MIN) = VOUT VIN(MAX )f = 1 . 8V = 327n s 22V(250kHz)
The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances:
R SENSE
80mV 0 . 012 5 . 84A
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. The power dissipation on the top side MOSFET can be easily estimated. Choosing a Fairchild FDS6982S dual MOSFET results in: RDS(ON) = 0.035 /0.022 , C MILLER = 215pF. At maximum input voltage with T(estimated) = 50C:
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PMAIN = 1 . 8V 2 (5) [1+ (0 . 005)(50 C - 25 C)] * 22V 5A (0 . 0 3 5) + (22V )2 ( 4)(215pF ) * 2 1 1 5 - 2 . 3 + 2 . 3 ( 300kHz ) = 332mW
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A short-circuit to ground will result in a folded back current of:
ISC = 25mV 1 120ns(22V) - = 2 . 1A 0 . 01 2 3 . 3 H
with a typical value of RDS(ON) and = (0.005/C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET is:
PSYNC = 22V - 1 . 8 V (2 . 1A )2 (1 . 125) (0 . 022) 22V = 100mW
which is less than under full-load conditions. CIN is chosen for an RMS current rating of at least 3A at temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02 for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR ( I L) = 0.02 (1.67A) = 33mV
P-P
38341f
21
LTC3834-1
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 8. The Figure 9 illustrates the current waveforms present in the various branches of the synchronous regulator operating in the continuous mode. Check the following in your layout: 1. Is the top N-channel MOSFET M1 located within 1cm of CIN? 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (-) terminals. The path formed by the top N-channel MOSFET, Schottky diode and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (-) terminals should be connected as close as possible to the (-) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 3. Does the LTC3834-1 VFB pin resistive divider connect to the (+) terminals of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s).
TRACK/SS L1 SENSE+ TG RSENSE VOUT
SW SENSE- LTC3834EGN-1 BOOST VFB PLLLPF fIN PLLIN/MODE RUN ITH SGND INTVCC PGND VIN BG
+
CINTVCC
VIN
Figure 8. LTC3834-1 Recommended Printed Circuit Layout Diagram
38341f
22
+
U
4. Are the SENSE - and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE - should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. 5. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1F ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance substantially. 6. Keep the switching node (SW), top gate node (TG), and boost node (BOOST) away from sensitive small-signal nodes, especially from the opposites channel's voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the "output side" of the LTC3834-1 and occupy minimum PC trace area. 7. Use a modified "star ground" technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC.
CB M1 M2 D1 Optional RIN DB CVIN GND CIN
3834-1 F08
W
UU
1F CERAMIC
COUT
+
LTC3834-1
APPLICATIO S I FOR ATIO U
SW L1 RSENSE VOUT D1 COUT RL1
3834-1 F09
VIN
RIN CIN
BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH.
PC Board Layout Debugging It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold--typically 10% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If prob-
W
UU
Figure 9. Branch Current Waveforms
lems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the SGND pin of the IC. An embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor--don't worry, the regulator will still maintain control of the output voltage.
38341f
23
LTC3834-1
TYPICAL APPLICATIO S
High Efficiency 9.5V, 3A Step-Down Converter
PLLLPF 0.01F RUN TRACK/SS BOOST ITH 560pF 105k 100pF SGND 39.2k PLLIN/MODE VFB 432k 22pF SENSE- SENSE+ PGND BG INTVCC 4.7F M2 COUT 150F LTC3834-1 SW VIN TG M1 CB 0.22F L1 7.2H CIN 10F VIN 10V TO 36V
M1, M2: Si4840DY L1: CDEP105-7R2M COUT: SANYO 10TPD150M
0.01
1000pF 48.7k 100pF SGND 68.1k
84.5k 100pF
M1, M2: Si4840DY L1 TOKO 053LC A915AY-3R3M
24
U
0.015
VOUT 9.5V 3A
38341 TA02
High Efficiency 12V to 1.8V, 2A Step-Down Converter
PLLLPF RUN TRACK/SS BOOST ITH LTC3834-1 SW VIN TG M1 CB 0.22F TBD CIN 10F VIN 12V
TBD
VOUT 1.8V 2A
INTVCC 4.7F BG M2
PLLIN/MODE VFB SENSE- SENSE+ PGND
COUT 100F CERAMIC
38341 TA03
38341f
LTC3834-1
TYPICAL APPLICATIO S
High Efficiency 5V, 5A Step-Down Converter
PLLLPF 0.01F RUN TRACK/SS BOOST ITH 560pF 54k 150pF SGND 69.8k PLLIN/MODE VFB 365k SENSE- 39pF SENSE+ PGND BG INTVCC 4.7F M2 LTC3834-1 SW VIN TG M1 CB 0.22F L1 3.3H CIN 10F VIN 5.5V TO 36V
M1, M2: Si4840DY L1: CDEP105-3R2M COUT: SANYO 10TPD150M
GND 0.01F
2.2nF 26.1k 100pF
68.1k
34k 390pF
M1, M2: Si4840DY L1: CDEP105-2R2M COUT: SANYO 10TPD150M
U
0.012
VOUT 5V 5A COUT 150F
38341 TA04
High Efficiency 1.2V, 5A Step-Down Converter
PLLLPF RUN TRACK/SS BOOST ITH LTC3834-1 SW VIN TG M1 CB 0.22F L1 2.2H CIN 10F VIN 4V TO 36V
0.012
VOUT 1.2V 5A COUT 150F x 2
SGND PLLIN/MODE VFB SENSE- SENSE+
INTVCC 4.7F BG M2
PGND
38341 TA05
38341f
25
LTC3834-1
PACKAGE DESCRIPTIO U
DHC Package 16-Lead Plastic DFN (5mm x 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05 3.50 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 4.40 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 0.10 (2 SIDES) R = 0.20 TYP 3.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 8 0.200 REF 0.75 0.05 4.40 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1 0.25 0.05 0.50 BSC 1.65 0.10 (2 SIDES) PIN 1 NOTCH
(DHC16) DFN 1103
1.65 0.05 2.20 0.05 (2 SIDES)
R = 0.115 TYP 9 16
0.40 0.10
0.00 - 0.05
38341f
26
LTC3834-1
PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.254 MIN
.150 - .165
.229 - .244 (5.817 - 6.198)
.0165 .0015
.150 - .157** (3.810 - 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
23
4
56
7
8
.004 - .0098 (0.102 - 0.249)
.015 .004 x 45 (0.38 0.10)
.007 - .0098 (0.178 - 0.249) 0 - 8 TYP
.0532 - .0688 (1.35 - 1.75)
.016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
38341f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3834-1
TYPICAL APPLICATIO
0.01F
560pF 54k 150pF SGND 68.1k
215k 39pF
M1, M2: Si4840DY L1: CDEP 105-3R2M COUT: SANYO 10TPD150M
RELATED PARTS
PART NUMBER LTC1735 LTC1778/LTC1778-1 LTC3708 LTC3727/LTC3727-1 LTC3728 LTC3729 LTC3731 LT3800 LTC3826/LTC3826-1 LTC3827/LTC3827-1 LTC3835/LTC3835-1 LT3844 LTC3845 LTC3850 DESCRIPTION High Efficiency Synchronous Step-Down Switching Regulator No RSENSE Current Mode Synchronous Step-Down Controllers Dual, 2-Phase, DC/DC Controller with Output Tracking High Efficiency, 2-Phase, Synchronous Step-Down Switching Regulators Dual, 550kHz, 2-Phase Synchronous Step-Down Controller 20A to 200A, 550kHz PolyPhase Synchronous Controller 3- to 12-Phase Step-Down Synchronous Controller High Voltage Synchronous Regulator Controller 30A IQ, Dual, 2-Phase Synchronous Step-Down Controller Low IQ Dual Synchronous Controllers Low IQ Synchronous Step-Down Controller High Voltage Current Mode Controller with Programmable Operating Frequency Low IQ Synchronous Step-Down Controller Dual, 2-Phase Synchronous Step-Down DC/DC Controller COMMENTS Output Fault Protection, 16-Pin SSOP Up to 97% Efficiency, 4V V IN 36V, 0.8V V OUT (0.9)(V IN), IOUT Up to 20A Current Mode, No RSENSE, Up/Down Tracking, Synchronizable 2-Phase Operation; 4V V IN 36V, 0.8V V OUT 14V, 99% Duty Cycle, 5mm x 5mm QFN, SSOP-28 Dual 180 Phased Controllers, VIN 3.5V to 35V, 99% Duty Cycle, 5mm x 5mm QFN Package, SSOP-28 Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Components, VIN Up to 36V 60A to 240A Output Current, 0.6V V OUT 6V, 4.5V V IN 32V VIN up to 60V, IOUT 20A, Current Mode, Onboard Bias Regulator, Burst Mode Operation, 16-Lead TSSOP Package 2-Phase Operation; 30A One Channel No Load IQ (50A Total), 4V V IN 36V, 0.8V V OUT 10V 2-Phase Operation; 115A Total No Load IQ, 4V V IN 36V 80A No Load IQ with One Channel On 80A No Load IQ, 4V V IN 36V, 0.8V V OUT 10V VIN up to 60V, IOUT 5A Onboard Bias Regulator, Burst Mode Operation, Sync Capability, 16-Lead TSSOP Package 4V V IN 60V, 1.23V V OUT 36V, 120A Quiescent Current 2-Phase Operation; 4V V IN 24V, 95% Efficiency, No RSENSE Option, IOUT Up to 20A, 4mm x 4mm QFN
No RSENSE is a trademark of Linear Technology Corporation. PolyPhase is a registered trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
U
PLLLPF RUN TRACK/SS BOOST ITH LTC3834-1 SW DB CMDSH-3 INTVCC 4.7F BG L1 3.2H 0.012 VOUT 3.3V 5A COUT 150F VIN TG CB 0.22F CIN 10F VIN 4V TO 36V PLLIN/MODE VFB SENSE- SENSE+ PGND
38341 TA06
Figure 10. High Efficiency 3.3V, 5A Step-Down Converter
38341f LT 1107 * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2007

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